Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.6aae89052f7e439b8fc06bd5cc6445b6.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-12T01:24:21 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=206
  • AGG_IO=206
  • AGG_SLICE=1204
  • NUM_4_INPUT_LUT=1794
  • NUM_BONDED_IBUF=90
  • NUM_BONDED_IOB=116
  • NUM_BUFGMUX=4
  • NUM_CYMUX=300
  • NUM_DCM=1
  • NUM_IOB_FF=33
  • NUM_LUT_RT=156
  • NUM_RAMB16BWE=9
  • NUM_SHIFT=1
  • NUM_SLICEL=1201
  • NUM_SLICEM=3
  • NUM_SLICE_FF=1294
  • NUM_XOR=270
NetStatistics
  • NumNets_Active=2585
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=122
  • NumNodesOfType_Active_BRAMDUMMY=16
  • NumNodesOfType_Active_CLKPIN=829
  • NumNodesOfType_Active_CNTRLPIN=865
  • NumNodesOfType_Active_DOUBLE=4827
  • NumNodesOfType_Active_DUMMY=4882
  • NumNodesOfType_Active_DUMMYBANK=115
  • NumNodesOfType_Active_DUMMYESC=50
  • NumNodesOfType_Active_GLOBAL=204
  • NumNodesOfType_Active_HFULLHEX=60
  • NumNodesOfType_Active_HLONG=18
  • NumNodesOfType_Active_HUNIHEX=355
  • NumNodesOfType_Active_INPUT=5839
  • NumNodesOfType_Active_IOBOUTPUT=71
  • NumNodesOfType_Active_OMUX=2414
  • NumNodesOfType_Active_OUTPUT=2247
  • NumNodesOfType_Active_PREBXBY=1721
  • NumNodesOfType_Active_VFULLHEX=307
  • NumNodesOfType_Active_VLONG=67
  • NumNodesOfType_Active_VUNIHEX=373
  • NumNodesOfType_Gnd_BRAMADDR=1
  • NumNodesOfType_Gnd_BRAMDUMMY=45
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_DOUBLE=28
  • NumNodesOfType_Gnd_DUMMY=2
  • NumNodesOfType_Gnd_DUMMYBANK=4
  • NumNodesOfType_Gnd_INPUT=61
  • NumNodesOfType_Gnd_OMUX=33
  • NumNodesOfType_Gnd_OUTPUT=22
  • NumNodesOfType_Gnd_PREBXBY=6
  • NumNodesOfType_Gnd_VFULLHEX=5
  • NumNodesOfType_Vcc_BRAMDUMMY=45
  • NumNodesOfType_Vcc_CNTRLPIN=5
  • NumNodesOfType_Vcc_DUMMY=2
  • NumNodesOfType_Vcc_INPUT=71
  • NumNodesOfType_Vcc_PREBXBY=16
  • NumNodesOfType_Vcc_VCCOUT=61
SiteStatistics
  • IBUF-DIFFMI_NDT=1
  • IBUF-DIFFMLR=28
  • IBUF-DIFFMTB=16
  • IBUF-DIFFSI_NDT=1
  • IBUF-DIFFSLR=26
  • IBUF-DIFFSTB=16
  • IOB-DIFFMLR=27
  • IOB-DIFFMTB=29
  • IOB-DIFFSLR=32
  • IOB-DIFFSTB=28
  • SLICEL-SLICEM=532
SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=1
  • DCM_DCM=1
  • IBUF=90
  • IBUF_DELAY_ADJ_BBOX=90
  • IBUF_IFF1=3
  • IBUF_INBUF=90
  • IBUF_PAD=90
  • IOB=116
  • IOB_DELAY_ADJ_BBOX=24
  • IOB_IFF1=18
  • IOB_INBUF=24
  • IOB_OFF1=12
  • IOB_OUTBUF=116
  • IOB_PAD=116
  • RAMB16BWE=9
  • RAMB16BWE_RAMB16BWE=9
  • SLICEL=1201
  • SLICEL_C1VDD=69
  • SLICEL_C2VDD=64
  • SLICEL_CYMUXF=153
  • SLICEL_CYMUXG=147
  • SLICEL_F=881
  • SLICEL_F5MUX=91
  • SLICEL_F6MUX=1
  • SLICEL_FFX=716
  • SLICEL_FFY=577
  • SLICEL_G=908
  • SLICEL_GNDF=84
  • SLICEL_GNDG=83
  • SLICEL_XORF=137
  • SLICEL_XORG=133
  • SLICEM=3
  • SLICEM_F=2
  • SLICEM_F5MUX=2
  • SLICEM_F6MUX=2
  • SLICEM_FFY=1
  • SLICEM_G=3
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[9:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
IBUF
  • ICE=[ICE:2] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:3]
  • SR=[SR:0] [SR_INV:3]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:90]
  • IBUF_DELAY_VALUE=[DLY0:90]
  • IFD_DELAY_VALUE=[DLY0:87] [DLY5:3]
  • SEL_IN=[SEL_IN:90] [SEL_IN_INV:0]
IBUF_IFF1
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:3] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:2] [INIT1:1]
  • IFF1_SR_ATTR=[SRLOW:2] [SRHIGH:1]
  • IFFATTRBOX=[ASYNC:1] [SYNC:2]
  • LATCH_OR_FF=[FF:3]
  • SR=[SR:0] [SR_INV:3]
IBUF_PAD
  • IOATTRBOX=[LVTTL:90]
IOB
  • ICE=[ICE:18] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:18]
  • O1=[O1_INV:2] [O1:114]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:12]
  • SR=[SR:12] [SR_INV:0]
  • T1=[T1_INV:8] [T1:16]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:24]
  • IBUF_DELAY_VALUE=[DLY0:24]
  • IFD_DELAY_VALUE=[DLY0:6] [DLY5:18]
  • SEL_IN=[SEL_IN:24] [SEL_IN_INV:0]
IOB_IFF1
  • CE=[CE:18] [CE_INV:0]
  • CK=[CK:18] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:18]
  • LATCH_OR_FF=[FF:18]
IOB_OFF1
  • CK=[CK:12] [CK_INV:0]
  • D=[D:12] [D_INV:0]
  • LATCH_OR_FF=[FF:12]
  • OFF1_INIT_ATTR=[INIT1:12]
  • OFF1_SR_ATTR=[SRHIGH:12]
  • OFFATTRBOX=[SYNC:12]
  • SR=[SR:12] [SR_INV:0]
IOB_OUTBUF
  • IN=[IN_INV:2] [IN:114]
  • SUSPEND=[3STATE:116]
  • TRI=[TRI_INV:8] [TRI:16]
IOB_PAD
  • DRIVEATTRBOX=[12:116]
  • IOATTRBOX=[LVTTL:116]
  • SLEW=[SLOW:116]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:9]
  • ENA=[ENA_INV:0] [ENA:9]
  • SSRA=[SSRA_INV:0] [SSRA:9]
  • WEA0=[WEA0:9] [WEA0_INV:0]
  • WEA1=[WEA1:9] [WEA1_INV:0]
  • WEA2=[WEA2:9] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:9]
  • WEB0=[WEB0:0] [WEB0_INV:9]
  • WEB1=[WEB1:0] [WEB1_INV:9]
  • WEB2=[WEB2_INV:9] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:9]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:9]
  • DATA_WIDTH_A=[1:8] [9:1]
  • DATA_WIDTH_B=[0:9]
  • ENA=[ENA_INV:0] [ENA:9]
  • SSRA=[SSRA_INV:0] [SSRA:9]
  • WEA0=[WEA0:9] [WEA0_INV:0]
  • WEA1=[WEA1:9] [WEA1_INV:0]
  • WEA2=[WEA2:9] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:9]
  • WEB0=[WEB0:0] [WEB0_INV:9]
  • WEB1=[WEB1:0] [WEB1_INV:9]
  • WEB2=[WEB2_INV:9] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:9]
  • WRITE_MODE_A=[WRITE_FIRST:9]
  • WRITE_MODE_B=[WRITE_FIRST:9]
SLICEL
  • BX=[BX_INV:6] [BX:344]
  • BY=[BY:264] [BY_INV:15]
  • CE=[CE:436] [CE_INV:68]
  • CIN=[CIN_INV:0] [CIN:147]
  • CLK=[CLK:766] [CLK_INV:18]
  • SR=[SR:233] [SR_INV:68]
SLICEL_CYMUXF
  • 0=[0:153] [0_INV:0]
  • 1=[1_INV:0] [1:153]
SLICEL_CYMUXG
  • 0=[0:147] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:90] [S0_INV:1]
SLICEL_F6MUX
  • S0=[S0:1] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:398] [CE_INV:64]
  • CK=[CK:708] [CK_INV:8]
  • D=[D:711] [D_INV:5]
  • FFX_INIT_ATTR=[INIT0:701] [INIT1:15]
  • FFX_SR_ATTR=[SRLOW:707] [SRHIGH:9]
  • LATCH_OR_FF=[FF:716]
  • REV=[REV_INV:0] [REV:130]
  • SR=[SR:213] [SR_INV:57]
  • SYNC_ATTR=[ASYNC:673] [SYNC:43]
SLICEL_FFY
  • CE=[CE:391] [CE_INV:64]
  • CK=[CK:559] [CK_INV:18]
  • D=[D:562] [D_INV:15]
  • FFY_INIT_ATTR=[INIT0:568] [INIT1:9]
  • FFY_SR_ATTR=[SRLOW:570] [SRHIGH:7]
  • LATCH_OR_FF=[FF:577]
  • SR=[SR:96] [SR_INV:47]
  • SYNC_ATTR=[ASYNC:538] [SYNC:39]
SLICEL_XORF
  • 1=[1_INV:0] [1:137]
SLICEM
  • BX=[BX_INV:0] [BX:2]
  • BY=[BY:3] [BY_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
SLICEM_F
  • LUT_OR_MEM=[LUT:2]
SLICEM_F5MUX
  • S0=[S0:2] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:2] [S0_INV:0]
SLICEM_FFY
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:1]
  • FFY_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[LUT:2] [RAM:1]
SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:1]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
IBUF
  • I=89
  • ICE=2
  • ICLK1=3
  • IQ1=3
  • PAD=90
  • SR=3
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=89
  • IFD_OUT=3
  • SEL_IN=90
IBUF_IFF1
  • CE=2
  • CK=3
  • D=3
  • Q=3
  • SR=3
IBUF_INBUF
  • IN=90
  • OUT=90
IBUF_PAD
  • PAD=90
IOB
  • I=24
  • ICE=18
  • ICLK1=18
  • IQ1=18
  • O1=116
  • OTCLK1=12
  • PAD=116
  • SR=12
  • T1=24
IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=24
  • IFD_OUT=18
  • SEL_IN=24
IOB_IFF1
  • CE=18
  • CK=18
  • D=18
  • Q=18
IOB_INBUF
  • IN=24
  • OUT=24
IOB_OFF1
  • CK=12
  • D=12
  • Q=12
  • SR=12
IOB_OUTBUF
  • IN=116
  • OUT=116
  • TRI=24
IOB_PAD
  • PAD=116
RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=9
  • ADDRA11=9
  • ADDRA12=9
  • ADDRA13=9
  • ADDRA2=8
  • ADDRA3=9
  • ADDRA4=9
  • ADDRA5=9
  • ADDRA6=9
  • ADDRA7=9
  • ADDRA8=9
  • ADDRA9=9
  • CLKA=9
  • DOA0=9
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=9
  • SSRA=9
  • WEA0=9
  • WEA1=9
  • WEA2=9
  • WEA3=9
  • WEB0=9
  • WEB1=9
  • WEB2=9
  • WEB3=9
RAMB16BWE_RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=9
  • ADDRA11=9
  • ADDRA12=9
  • ADDRA13=9
  • ADDRA2=8
  • ADDRA3=9
  • ADDRA4=9
  • ADDRA5=9
  • ADDRA6=9
  • ADDRA7=9
  • ADDRA8=9
  • ADDRA9=9
  • CLKA=9
  • DOA0=9
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=9
  • SSRA=9
  • WEA0=9
  • WEA1=9
  • WEA2=9
  • WEA3=9
  • WEB0=9
  • WEB1=9
  • WEB2=9
  • WEB3=9
SLICEL
  • BX=350
  • BY=279
  • CE=504
  • CIN=147
  • CLK=784
  • COUT=147
  • F1=874
  • F2=796
  • F3=483
  • F4=241
  • F5=2
  • FX=1
  • FXINA=1
  • FXINB=1
  • G1=901
  • G2=821
  • G3=487
  • G4=231
  • SR=301
  • X=400
  • XQ=716
  • Y=373
  • YQ=577
SLICEL_C1VDD
  • 1=69
SLICEL_C2VDD
  • 1=64
SLICEL_CYMUXF
  • 0=153
  • 1=153
  • OUT=153
  • S0=153
SLICEL_CYMUXG
  • 0=147
  • 1=147
  • OUT=147
  • S0=147
SLICEL_F
  • A1=874
  • A2=796
  • A3=483
  • A4=241
  • D=881
SLICEL_F5MUX
  • F=91
  • G=91
  • OUT=91
  • S0=91
SLICEL_F6MUX
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
SLICEL_FFX
  • CE=462
  • CK=716
  • D=716
  • Q=716
  • REV=130
  • SR=270
SLICEL_FFY
  • CE=455
  • CK=577
  • D=577
  • Q=577
  • SR=143
SLICEL_G
  • A1=901
  • A2=821
  • A3=487
  • A4=231
  • D=908
SLICEL_GNDF
  • 0=84
SLICEL_GNDG
  • 0=83
SLICEL_XORF
  • 0=137
  • 1=137
  • O=137
SLICEL_XORG
  • 0=133
  • 1=133
  • O=133
SLICEM
  • BX=2
  • BY=3
  • CLK=1
  • F1=2
  • F2=2
  • F3=2
  • F5=2
  • FX=1
  • FXINA=2
  • FXINB=2
  • G1=3
  • G2=3
  • G3=3
  • G4=2
  • SR=1
  • Y=1
  • YQ=1
SLICEM_F
  • A1=2
  • A2=2
  • A3=2
  • D=2
SLICEM_F5MUX
  • F=2
  • G=2
  • OUT=2
  • S0=2
SLICEM_F6MUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
SLICEM_FFY
  • CK=1
  • D=1
  • Q=1
SLICEM_G
  • A1=3
  • A2=3
  • A3=3
  • A4=2
  • D=3
  • DI=1
  • WS=1
SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSG=1
 
Software Quality
Run Statistics
Bitgen 12925 12924 0 0 0 0 0
MAP 7048 6850 0 0 0 0 0
NGDBuild 7365 7349 0 0 0 0 0
PAR 6842 6490 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74935 74931 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6496 6492 0 0 0 0 0
xst 7100 6997 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=15
NGDBUILD_NUM_FDC=16 NGDBUILD_NUM_FDCE=26 NGDBUILD_NUM_FDCPE=8 NGDBUILD_NUM_FDE=327
NGDBUILD_NUM_FDPE=2 NGDBUILD_NUM_FDR=21 NGDBUILD_NUM_FDRE=44 NGDBUILD_NUM_FDRSE=2
NGDBUILD_NUM_FDR_1=8 NGDBUILD_NUM_FDS=17 NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=11
NGDBUILD_NUM_IBUF=25 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=18 NGDBUILD_NUM_IOBUF=24
NGDBUILD_NUM_LUT1=9 NGDBUILD_NUM_LUT2=302 NGDBUILD_NUM_LUT2_D=1 NGDBUILD_NUM_LUT3=195
NGDBUILD_NUM_LUT3_D=4 NGDBUILD_NUM_LUT3_L=3 NGDBUILD_NUM_LUT4=355 NGDBUILD_NUM_LUT4_D=10
NGDBUILD_NUM_LUT4_L=13 NGDBUILD_NUM_MUXCY=9 NGDBUILD_NUM_MUXF5=87 NGDBUILD_NUM_MUXF6=2
NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=92 NGDBUILD_NUM_SRL16=1 NGDBUILD_NUM_VCC=7
NGDBUILD_NUM_XORCY=10
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=158 NGDBUILD_NUM_FDC=36
NGDBUILD_NUM_FDCE=154 NGDBUILD_NUM_FDCE_1=6 NGDBUILD_NUM_FDCP=128 NGDBUILD_NUM_FDCPE=8
NGDBUILD_NUM_FDC_1=10 NGDBUILD_NUM_FDE=715 NGDBUILD_NUM_FDP=12 NGDBUILD_NUM_FDPE=2
NGDBUILD_NUM_FDPE_1=2 NGDBUILD_NUM_FDR=21 NGDBUILD_NUM_FDRE=44 NGDBUILD_NUM_FDRSE=2
NGDBUILD_NUM_FDR_1=8 NGDBUILD_NUM_FDS=17 NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=22
NGDBUILD_NUM_IBUF=112 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=31 NGDBUILD_NUM_LUT1=9
NGDBUILD_NUM_LUT1_L=140 NGDBUILD_NUM_LUT2=578 NGDBUILD_NUM_LUT2_D=1 NGDBUILD_NUM_LUT2_L=96
NGDBUILD_NUM_LUT3=217 NGDBUILD_NUM_LUT3_D=4 NGDBUILD_NUM_LUT3_L=285 NGDBUILD_NUM_LUT4=417
NGDBUILD_NUM_LUT4_D=10 NGDBUILD_NUM_LUT4_L=30 NGDBUILD_NUM_MUXCY=14 NGDBUILD_NUM_MUXCY_L=286
NGDBUILD_NUM_MUXF5=93 NGDBUILD_NUM_MUXF6=2 NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=92
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